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ETPLL Embedded PLL Test

Datasheet

ETPLL provides unique and comprehensive IP for the digital characterization and production test of analog phase locked loops. ETPLL enables the on-chip testing of critical PLL parameters essential for the success of today’s timing critical, multi-clock domain ASICs.

ETPLL IP is non-invasive to the circuitry of the PLL. It only requires connections to the input and outputs of the PLL. A digital multiplexer allows test signals to be inserted into the input path without requiring connections to the analog nodes of the PLL. The ETPLL IP uses the reference input to the PLL as an initial stimulus. By processing clock outputs of the PLL, and a lock indicator (if used), ETPLL calculates jitter, loop gain, upper and lower lock range frequencies, and lock time. Jitter can be measured at ±1 sigma (RMS), ±N sigma, or peak-to-peak, and test data can be output to create a histogram of the jitter during characterization.

Test control parameters are serially shifted into the ETPLL IP to initiate the test. Upon test completion, binary-encoded upper and lower limits are shifted into the controller and the measured values are serially shifted out via the Test Access Port (TAP). Pass/fail bits are computed during the shift and are contained within the bit-stream for each limit comparison.

An IEEE-1149.1 TAP controller operates as the test manager for the design and the ETPLL IP for the analog PLL test. Using the TAP, the ETPLL IP can be accessed during manufacturing test and system verification phases of the host product. The ability to access this test capability at manufacturing and system deployment permits the re-use of the embedded test capability beyond silicon manufacturing, providing test value throughout the life of the OEM product.

It is recommended that ETPLL be used in conjunction with LogicVision's Silicon Insight real-time control and access software. The Silicon Insight software automatically executes the ETPLL controllers and then extracts and interprets all shifted out raw measurement values.

ETPLL includes a design kit that automatically generates, assembles, and verifies the ETPLL IP for the PLL design as well as the IEEE 1149.1 TAP and boundary scan logic. The automatic creation of verification test-benches enables the verification of the ETPLL configuration for the design in question. Conventional WGL or SVF patterns are provided.