ETBoundary
ETBoundary provides a complete solution for the creation and integration of boundary scan cells and related control logic for embedded test and diagnosis of integrated circuit (IC) semiconductor I/O as well as test and diagnosis of board-level interconnect nets between ICs. Access to the boundary scan cells is provided through LogicVision's Test Access Port (TAP) interface using the IEEE 1149.1 (JTAG) and IEEE 1149.6 (ACJTAG) protocols.
ETBoundary's highly automated integration flow reduces IC engineering development effort and improves time-to-market. ETBoundary automatically generates the RTL code for the TAP controller and boundary scan cells and automatically integrates these into the design RTL. It also generates the scripts required for logic synthesis of the RTL, a BSDL description of the boundary scan functionality, simulation testbenches to verify the correctness of the boundary scan, and test patterns for manufacturing test of the IC. This completely eliminates the design phase for boundary scan logic and I/O cells, and automates the integration and verification of the boundary scan solution.
ETBoundary options support standard 1149.1 boundary scan cells, 1149.1 custom boundary scan cells, and 1149.6 boundary scan cells for differential I/O cells driving AC-coupled nets. It also provides a unique 1149.1-based solution for contactless testing of I/O using boundary scan. In all cases, the boundary scan logic can be accessed throughout the life of the IC, including manufacturing test, silicon debug, and system verification. The result is that both I/O cell defects and inter-IC board interconnect problems are detected prior to shipment, reducing field support costs and increasing customer satisfaction.